CA1126871A - Private cache to cpu interface in a bus oriented system - Google Patents

Private cache to cpu interface in a bus oriented system

Info

Publication number
CA1126871A
CA1126871A CA315,761A CA315761A CA1126871A CA 1126871 A CA1126871 A CA 1126871A CA 315761 A CA315761 A CA 315761A CA 1126871 A CA1126871 A CA 1126871A
Authority
CA
Canada
Prior art keywords
bus
memory
signal
data
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA315,761A
Other languages
English (en)
French (fr)
Inventor
Thomas F. Joyce
Thomas O. Holtey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1126871A publication Critical patent/CA1126871A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
CA315,761A 1977-12-22 1978-11-02 Private cache to cpu interface in a bus oriented system Expired CA1126871A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/863,097 US4161024A (en) 1977-12-22 1977-12-22 Private cache-to-CPU interface in a bus oriented data processing system
US863,097 1977-12-22

Publications (1)

Publication Number Publication Date
CA1126871A true CA1126871A (en) 1982-06-29

Family

ID=25340243

Family Applications (1)

Application Number Title Priority Date Filing Date
CA315,761A Expired CA1126871A (en) 1977-12-22 1978-11-02 Private cache to cpu interface in a bus oriented system

Country Status (8)

Country Link
US (1) US4161024A (en])
JP (1) JPS5492027A (en])
AU (1) AU518637B2 (en])
CA (1) CA1126871A (en])
DE (1) DE2854485C2 (en])
FR (1) FR2412888B1 (en])
GB (1) GB2011678B (en])
YU (1) YU40212B (en])

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US4458310A (en) * 1981-10-02 1984-07-03 At&T Bell Laboratories Cache memory using a lowest priority replacement circuit
US4466059A (en) * 1981-10-15 1984-08-14 International Business Machines Corporation Method and apparatus for limiting data occupancy in a cache
US4503501A (en) * 1981-11-27 1985-03-05 Storage Technology Corporation Adaptive domain partitioning of cache memory space
US4430712A (en) 1981-11-27 1984-02-07 Storage Technology Corporation Adaptive domain partitioning of cache memory space
US4476526A (en) * 1981-11-27 1984-10-09 Storage Technology Corporation Cache buffered memory subsystem
US4887235A (en) * 1982-12-17 1989-12-12 Symbolics, Inc. Symbolic language data processing system
DE3302929A1 (de) * 1983-01-28 1984-08-02 Siemens AG, 1000 Berlin und 8000 München Speicherprogrammierbare steuerung
US4837785A (en) * 1983-06-14 1989-06-06 Aptec Computer Systems, Inc. Data transfer system and method of operation thereof
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
DE3502147A1 (de) 1984-01-23 1985-08-08 Hitachi Microcomputer Engineering Ltd., Kodaira, Tokio/Tokyo Datenverarbeitungssystem mit verbesserter pufferspeichersteuerung
JPS60229111A (ja) * 1984-04-26 1985-11-14 Fanuc Ltd 数値制御方式
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
US4814981A (en) * 1986-09-18 1989-03-21 Digital Equipment Corporation Cache invalidate protocol for digital data processing system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
JPS6452912U (en]) * 1987-09-30 1989-03-31
US5119290A (en) * 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
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US4972313A (en) * 1989-08-07 1990-11-20 Bull Hn Information Systems Inc. Bus access control for a multi-host system using successively decremented arbitration delay periods to allocate bus access among the hosts
DE69123987T2 (de) * 1990-01-31 1997-04-30 Hewlett Packard Co Stossbetrieb für Mikroprozessor mit externem Systemspeicher
US5062045A (en) * 1990-02-23 1991-10-29 International Business Machines Corporation System for maintaining a document and activity selective alterable document history log in a data processing system
US5119493A (en) * 1990-02-23 1992-06-02 International Business Machines Corporation System for recording at least one selected activity from a selected resource object within a distributed data processing system
US5778423A (en) * 1990-06-29 1998-07-07 Digital Equipment Corporation Prefetch instruction for improving performance in reduced instruction set processor
US5289581A (en) * 1990-06-29 1994-02-22 Leo Berenguel Disk driver with lookahead cache
US5249281A (en) * 1990-10-12 1993-09-28 Lsi Logic Corporation Testable ram architecture in a microprocessor having embedded cache memory
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5524250A (en) * 1991-08-23 1996-06-04 Silicon Graphics, Inc. Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers
US5528764A (en) * 1992-12-24 1996-06-18 Ncr Corporation Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
US6226722B1 (en) * 1994-05-19 2001-05-01 International Business Machines Corporation Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing
US5963973A (en) * 1996-12-16 1999-10-05 Bull Hn Information Systems Inc. Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data
US5809514A (en) * 1997-02-26 1998-09-15 Texas Instruments Incorporated Microprocessor burst mode data transfer ordering circuitry and method
US6360282B1 (en) * 1998-03-25 2002-03-19 Network Appliance, Inc. Protected control of devices by user applications in multiprogramming environments
US20170371783A1 (en) * 2016-06-24 2017-12-28 Qualcomm Incorporated Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system

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US3786427A (en) * 1971-06-29 1974-01-15 Ibm Dynamic address translation reversed
US3820078A (en) * 1972-10-05 1974-06-25 Honeywell Inf Systems Multi-level storage system having a buffer store with variable mapping modes
US4016541A (en) * 1972-10-10 1977-04-05 Digital Equipment Corporation Memory unit for connection to central processor unit and interconnecting bus
US3949375A (en) * 1973-02-14 1976-04-06 Dma Data Industries, Inc. Computer automated information system
US3810110A (en) * 1973-05-01 1974-05-07 Digital Equipment Corp Computer system overlap of memory operation
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US3973244A (en) * 1975-02-27 1976-08-03 Zentec Corporation Microcomputer terminal system
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system

Also Published As

Publication number Publication date
GB2011678B (en) 1982-03-24
DE2854485C2 (de) 1986-02-06
FR2412888B1 (fr) 1986-09-05
FR2412888A1 (fr) 1979-07-20
JPS6327738B2 (en]) 1988-06-06
AU4254078A (en) 1979-06-28
US4161024A (en) 1979-07-10
JPS5492027A (en) 1979-07-20
GB2011678A (en) 1979-07-11
DE2854485A1 (de) 1979-07-05
YU40212B (en) 1985-08-31
YU302278A (en) 1982-06-30
AU518637B2 (en) 1981-10-08

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